Opal Kelly has support information for using MicroBlaze with their boards on their website but I was unable to get it to work. Their example uses EDK version 8.2 and the XEM3010-1500 boards. I am using EDK 12.1 and the XEM3001 board.
Here are my notes for how I was able to run the MicroBlaze on the XEM3001 board and integrate it with my top level verilog code.
Create a New Project in Xilinx ISE (12.1). I am using the Opal Kelly XEM3001 board, so the project settings are, Family = Spartan3, Device = XC3S400, Package = PQ208, Speed = -4, and my Preferred Language is Verilog.
Add a top level HDL module and .ucf files from a previous project or the First example from Opal Kelly, as well as the okLibrary.v file.
Copy the Opal Kelly .ngc files to your project directory.
Add a New Source and select Embedded Processor. This will launch Xilinx Platform Studio.
In Base System Builder:
- create a new design
- I would like to create a system for a custom board
- Single-Processor System
- Reference Clock Frequency = 50 MHz, Processor Type = MicroBlaze, System Clock Frequency = 66.67 MHz, Local Memory = 16 KB
- don’t make any changes on Peripheral Configuration for now
- keep clicking next to finish the Base System Builder
From IP Catalog add two General Purpose IO Peripherals to be used for connecting to LEDS and Buttons on the Opal Kelly board. Change the names for xps_gpio_0 & xps_gpio_1 to leds & buttons. Connect them to mb_plb. On the ports tab, make external connections for the leds & buttons. On the Addresses tab click Generate Addresses.
In the Hardware menu, Generate Netlist
In the Software Menu, Add Software Application Project.
Add a new .c file to the Sources section of the project and write the code for your application.
Right click on the Project and select, Mark to Initialize BRAMs
In compiler options select no optimization (because my example uses a software delay)
Right click on the Project and select, Build Project
In ISE
- highlight the .xmp module in the Design Window
- double click View HDL Instantiation Template in the Processes window
- copy the Instantiation Template to your top level module and wire it up
- with the top module highlighted in the Design Window, double click Update Bitstream with Processor Data in the Processes window
- use Opal Kelly FrontPanel to download the download.bit file to the board and test it
The Verilog code:
`default_nettype none
`timescale 1ns / 1ps
module okTop(
input wire clk1,
input wire [7:0] hi_in,
output wire [1:0] hi_out,
inout wire [15:0] hi_inout,
output wire [7:0] led,
input wire [3:0] button
);
parameter DATA_WIDTH = 16;
wire [DATA_WIDTH-1:0] Version = 1;
// Opal Kelly Module Interface Connections
wire ti_clk;
wire [30:0] ok1;
wire [16:0] ok2;
wire [15:0] command_pulse; //command pulses from USB
wire reset_n = !command_pulse[0];
//wire reset = command_pulse[0];
wire reset = button[0];
wire run = command_pulse[1];
wire stop = command_pulse[2];
reg running;
// Instantiate the module
(* BOX_TYPE = “user_black_box” *)
mbTest instance_name (
.fpga_0_clk_1_sys_clk_pin(clk1),
.fpga_0_rst_1_sys_rst_pin(reset),
.buttons_GPIO_IO_I_pin(button),
.leds_GPIO_IO_O_pin(led)
);
//————————————————————————
// Instantiate the okHostInterface and connect endpoints to
// the Opal Kelly Module Interface
//————————————————————————
okHost hostIF(.hi_in(hi_in), .hi_out(hi_out), .hi_inout(hi_inout),
.ti_clk(ti_clk), .ok1(ok1), .ok2(ok2));
okTriggerIn trigIn53 (.ok1(ok1), .ep_addr(8′h53),
.ep_clk(ti_clk), .ep_trigger(command_pulse));
okWireOut ep3f (.ok1(ok1), .ok2(ok2), .ep_addr(8′h3f), .ep_datain(Version));
endmodule
The C code:
#include "xparameters.h"
#include "xgpio.h"
int main( void )
{
XGpio led, push;
int i, psb_check;
XGpio_Initialize( &led, XPAR_LEDS_DEVICE_ID );
XGpio_SetDataDirection( &led, 1, 0x00000000);
XGpio_Initialize( &push, XPAR_BUTTONS_DEVICE_ID );
XGpio_SetDataDirection( &push, 1, 0xffffffff);
int tmp;
int j;
while( 1 )
{
tmp = 1;
for( j = 1 ; j < 8 ; j++ )
{
XGpio_DiscreteWrite( &led, 1, ~tmp );
tmp *= 2;
for( i=0 ; i < 999999 ; i++ );
}
}
}
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