Posts Tagged ‘Xilinx’

Xilinx MicroBlaze Embedded Processor On Opal Kelly Board

June 22, 2010

Opal Kelly has support information for using MicroBlaze with their boards on their website but I was unable to get it to work. Their example uses EDK version 8.2 and the XEM3010-1500 boards. I am using EDK 12.1 and the XEM3001 board.

Here are my notes for how I was able to run the MicroBlaze on the XEM3001 board and integrate it with my top level verilog code.

Create a New Project in Xilinx ISE (12.1).  I am using the Opal Kelly XEM3001 board, so the project settings are, Family = Spartan3, Device = XC3S400, Package = PQ208, Speed = -4, and my Preferred Language is Verilog.

Add a top level HDL module and .ucf files from a previous project or the First example from Opal Kelly, as well as the okLibrary.v file.

Copy the Opal Kelly .ngc files to your project directory.

Add a New Source and select Embedded Processor. This will launch Xilinx Platform Studio.

In Base System Builder:
- create a new design
- I would like to create a system for a custom board
- Single-Processor System
- Reference Clock Frequency = 50 MHz, Processor Type = MicroBlaze, System Clock Frequency = 66.67 MHz, Local Memory = 16 KB
- don’t make any changes on Peripheral Configuration for now
- keep clicking next to finish the Base System Builder

From IP Catalog add two General Purpose IO Peripherals to be used for connecting to LEDS and Buttons on the Opal Kelly board. Change the names for xps_gpio_0 & xps_gpio_1 to leds & buttons. Connect them to mb_plb. On the ports tab, make external connections for the leds & buttons. On the Addresses tab click Generate Addresses.

In the Hardware menu, Generate Netlist

In the Software Menu, Add Software Application Project.
Add a new .c file to the Sources section of the project and write the code for your application.
Right click on the Project and select, Mark to Initialize BRAMs
In compiler options select no optimization (because my example uses a software delay)
Right click on the Project and select, Build Project

In ISE
- highlight the .xmp module in the Design Window
- double click View HDL Instantiation Template in the Processes window
- copy the Instantiation Template to your top level module and wire it up
- with the top module highlighted in the Design Window, double click Update Bitstream with Processor Data in the Processes window
- use Opal Kelly FrontPanel to download the download.bit file to the board and test it

The Verilog code:


`default_nettype none
`timescale 1ns / 1ps

module okTop(
input wire clk1,
input wire [7:0] hi_in,
output wire [1:0] hi_out,
inout wire [15:0] hi_inout,

output wire [7:0] led,
input wire [3:0] button
);

parameter DATA_WIDTH = 16;

wire [DATA_WIDTH-1:0] Version = 1;

// Opal Kelly Module Interface Connections
wire ti_clk;
wire [30:0] ok1;
wire [16:0] ok2;

wire [15:0] command_pulse; //command pulses from USB
wire reset_n = !command_pulse[0];
//wire reset = command_pulse[0];
wire reset = button[0];
wire run = command_pulse[1];
wire stop = command_pulse[2];

reg running;

// Instantiate the module
(* BOX_TYPE = “user_black_box” *)
mbTest instance_name (
.fpga_0_clk_1_sys_clk_pin(clk1),
.fpga_0_rst_1_sys_rst_pin(reset),
.buttons_GPIO_IO_I_pin(button),
.leds_GPIO_IO_O_pin(led)
);

//————————————————————————
// Instantiate the okHostInterface and connect endpoints to
// the Opal Kelly Module Interface
//————————————————————————
okHost hostIF(.hi_in(hi_in), .hi_out(hi_out), .hi_inout(hi_inout),
.ti_clk(ti_clk), .ok1(ok1), .ok2(ok2));

okTriggerIn trigIn53 (.ok1(ok1), .ep_addr(8′h53),
.ep_clk(ti_clk), .ep_trigger(command_pulse));

okWireOut ep3f (.ok1(ok1), .ok2(ok2), .ep_addr(8′h3f), .ep_datain(Version));

endmodule

The C code:

#include "xparameters.h"
#include "xgpio.h"

int main( void )
{
	XGpio led, push;
	int i, psb_check;

	XGpio_Initialize( &led, XPAR_LEDS_DEVICE_ID );
	XGpio_SetDataDirection( &led, 1, 0x00000000);

	XGpio_Initialize( &push, XPAR_BUTTONS_DEVICE_ID );
	XGpio_SetDataDirection( &push, 1, 0xffffffff);

	int tmp;
	int j;
	while( 1 )
	{
		tmp = 1;
		for( j = 1 ; j < 8 ; j++ )
		{
			XGpio_DiscreteWrite( &led, 1, ~tmp );
			tmp *= 2;

			for( i=0 ; i < 999999 ; i++ );
		}
	}
}

Click on the screenshots to go to flickr, then click the all sizes button at the top of the image to get to the high resolution version.

ise

xps_av

xps_ports

Avnet Spartan 3E Evaluation Kit

April 13, 2009

This was a project from 2006. I will have more to say about programming Xilinx FPGAs and using USB in the future, just not with the Avnet Spartan 3E Evaluation Kit. The end user is still using this, and this particular board dosen’t seem to be on the market anymore. Currently I am working with Opal Kelly and QuickUSB modules, for connecting custom electronics into the computer via USB.

Dec 13, 2006 – updated Jan 4, 2007

About 15 years ago I made a readout for a Mitutoyo caliper, by connecting it to an 8255 parallel I/O port on an 8085 board that I had designed and wire wrapped. The data returning from the caliper, was decoded by software running on the 8085. This software monitored the port looking for clock pulse edges. On the clock edge the state of the data line was recorded. By reading all the bits in this manner the position reading was constructed. A C program running on a PC read the position measurement from the 8085 board. The 8085 also performed other functions, like reading an ADC and running stepper motors.

About 10 years ago I did another interface using TTL logic chips, wire wrapped on an ISA card plugged into a 286 running MSDOS. A C++ program was written to read the position from this board as well as data from other instruments. That system is still being used, but now they want to use a modern computer running Windows XP, and not have to rely on the 286 running MSDOS.

The readout system is now being built to connect via USB. I chose to use the Avnet Spartan 3E Evaluation Kit.

IMG_1340

The PROM for the Cypress USB Micro controller was replaced by QuickUSB firmware purchased from Bitwise Systems.

IMG_1342

With QuickUSB running the Avnet utility for configuring the FPGA will no longer function, so I borrowed an old Xilinx cable (can’t remember the name), but iMPACT 8.2 did not support this cable. By replacing the 0 ohm resistor on JT2 with a jumper I could switch between starting the Cypress chip with QuickUSB firmware or no firmware. By using a jumper on the board you can also reset the Cypress chip without unplugging the USB cable. This way you can be running in no firmware mode, to configure the FPGA using the Avnet utility. The jumper was changed and the cypress reset to start up with QuickUSB. I could then test my Windows code which reads the Mitutoyo position reading from my FPGA logic.

IMG_1970

IMG_1971

The vector board visible beneath the Avnet board just holds the jumper for selecting the Cypress chip firmware. An extra connector was added to the cable for clipping the scope probes on. It would have been easier if I could get ModelSim to work with ISE 8.2, to get my logic worked out before dumping it into the FPGA.

IMG_2439

The Xilinx Platform USB cable was obtained to make it easier to change the FPGA configuration. Downloading via the Platform USB cable fails when first starting the board with QuickUSB firmware. After the FPGA has been configured once with the board in Cypress with no firmware mode, it can then be reconfigured when the Cypress chip is running QuickUSB.

IMG_2440

The Mitutoyo signals were fed back out on other FPGA pins for looking at with the scope. Bad scope grounding gives wavy traces.

IMG_2443

Since it works, I cleaned up my cables.

IMG_2707

Getting my FPGA configuration into the SPI Flash memory on this board was a real nightmare. I am using ISE 8.2, but you need ISE 7.1 in order to generate a HEX file to use with the Avnet utility for Writing to the SPI Flash. What I didn’t realize, and what Avnet did not mention in their documentation was the need to do a bulk erase before doing a write.

You should be able to use iMPACT with the Platform Cable USB and flying leads connected to the SPI Flash connector on the Avnet board. Bugs in iMPACT 8.2 prevented this from working. There is also a utility xspi_usb which can be downloaded from the Xilinx website with should do the job, but it has the same bugs as iMPACT 8.2. Search for xapp445 in the documentation section of the Xilinx website.


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